The present invention relates to electronic circuits, and more particularly to conversion of supply voltages used in such circuits.
In integrated circuits (IC), there is often a need to generate a lower DC voltage from a higher DC supply voltage. One known circuit for achieving this is commonly referred to as pulse width modulated (PWM) buck regulator, a simplified block diagram of which is shown in FIG. 1. PWM buck regulator 100 of FIG. 1 is shown as including, in part, a PWM signal generator 105, a driver 110, and an analog feedback control loop 115. Feedback control loop 115, in turn, includes a comparator 125, and a frequency compensator 120. Supply voltage VDD is pulse-width modulated by PWM buck regulator 100 and is subsequently supplied as output voltage signal VOUT. LC filter 130 is adapted to filter out the high frequency components of noise of voltage signal VOUT. Both LC filter 130 and resistive load 140 are typically external to PWM buck regulator 100.
Feedback control loop 115 is adapted to maintain VOUT nearly equal to reference voltage VR and further to maintain stability in the loop. Frequency compensator 120 is sensitive to variations in the reactive loads present at node 135 carrying signal VOUT. Therefore, frequency compensator 120 is typically difficult to design and often requires components external to PWM buck regulator 100 if the external load seen by node 135 is not purely resistive. Such external components increase both the complexity as well as the cost of PWM buck regulator 100. PWM signal generator 105 is shown as including an oscillator 102, and a comparator 104.
FIG. 2 is a simplified block diagram of RC oscillator 102 of FIG. 1, as known in the prior art. If signals Q and Q are respectively at logic low and high states, switch 166 is open and switch 164 is closed, causing current source 150 to charge capacitor 168 thereby to increase voltage VM. If signals Q and Q are respectively at logic high and low states, switch 166 is closed and switch 164 is open, causing current source 152 to discharge capacitor 168 thereby to decrease voltage VM. Latch 165 is set or reset in response to the comparison operations performed by comparators 156 and 158. As seen from FIG. 2, comparator 156 compares voltage VM with the high reference voltages VH, and comparator 158 compares voltage VM with the low reference voltages VL.
FIG. 3A shows the variations in voltage VM as a function of time. FIG. 3B shows the change in the logic states of signals Q and Q as a function of time. Time periods T1 and T2 shown in FIGS. 3A and 3B are defined by the following equations:
            T      1        =                  C                  I          1                    ⁢              (                              V            H                    -                      V            L                          )                        T      2        =                  C                  I          2                    ⁢              (                              V            H                    -                      V            L                          )            where C is the capacitance of capacitor 168, I1 is the current that flow through current source 150, and I1 is the current that flow through current source 152.
To overcome the above-described drawbacks of PWM buck regulator 100, PWM buck regulator with hysteretic control has been developed. FIG. 4 is a simplified high-level block diagram of a hysteretic PWM buck regulator 200, as known in the prior art. Hysteretic PWM buck regulator 200 includes, in part, a driver 210 and a hysteresis comparator 220. RC filter 230 and resistive load 240 are external components. The high frequency component of the noise generated by driver 210 is filtered by LC filter 230 and is supplied as output voltage signal VOUT via node 235.
Hysteretic PWM buck regulator 200 is operative to self-oscillate. As shown in FIG. 5A, output voltage VOUT varies between and is nearly equal to the average of voltage levels VH and VL—applied to the two input terminals of hysteresis comparator 220. Due, in part, to the DC offset of hysteresis comparator 220, it is relatively difficult to keep voltage levels VH and VL close to one another. Furthermore, as is known, it is desirable to operate hysteretic PWM buck regulator 200 at relatively high frequencies to keep the values of the capacitor 232, and inductor 234 disposed in LC filter 230 small. As the frequency of operation increases, the delay across hysteresis comparator 220 causes output voltage Vout to overshoot VH and undershoot VL, as shown in FIG. 5B, thereby further increasing the ripple at the output voltage and rendering it difficult to control.